NAME: Ritu Jain
DESIGNATION :   Assistant Professor
QUALIFICATION :  

  • M. Tech. (VLSI Design), Rajasthan Technical University, 2015
  • B. Tech. (Electronics and Communication), Banasthali University, 2011.

OVERVIEW OF PROFILE:

Ms. Ritu Jain is an Assistant Professor in the School of E&TC Engineering. Her inter- disciplinary research interests cover VLSI Front End and Back End Design.

Fore Front Area of Research: VLSI Back End Design
Email id : ritu.jain@mitaoe.ac.in
Contact no: 020-30253500 Ext:
Experience  : Teaching – 3.5 years Industry – 2.5 years


  • Awarded by ‘PAT ON THE BACK’ award at E—infochips

PUBLICATIONS

  • Ritu Jain, Dinesh Chand Gupta “Design and Analysis of Generic Architecture of Multipliers” “International Journal of Engineering Research & Technology” ISSN: 2278-0181
  • Ritu Jain, Swpnil Jain “Leakage Power Estimation and minimization in a 6T SRAM Cell using Dual Vth, Dual Tox, and stacking techniques” in International Journal of Electronics and Communication Technology (IJECT)”.

WORKSHOPS CONDUCTED

  • “Recent trends in FPGA & Embedded Systems”, at LDRP Institute of Technology & Research, Ahmedabad on 16th and 17th February, 2016
  • “An Expert talk on Verilog”, at Parul University, Vadodara, on 3rd and 4th March, 2016